In digital systems, bidirectional busses are often used to transmit data and control signals back and forth across various sub-systems.
In order to reduce the number of physical busses required to realize a desired level of functionality, such busses are often shared by time multiplexing. It is known that a time multiplexed bus, with two sets of drivers/receivers, can achieve functional equivalence to two separate busses, provided that both sets of drivers are not simultaneously active.
If two separate bus drivers are active concurrently, and especially if each set of drivers attempts to force the bus voltage levels to different digital values, bus contention results. In such a situation, the voltage level on the bus can attain forbidden, non-specified, or indeterminate values. Typically, the propagation delay also increases significantly in such a situation.
In conventional TTL bus design, a "Tri-State" or "High Impedance" driver design methodology allows multiple drivers to share a common bus. A "normal" TTL driver sources current when it is at a high level and sinks current when it is at a low level. By contrast, a "tri-stated" TTL driver neither sources nor sinks current in both high and low levels. In electronic terms, a tri-stated driver behaves like a high impedance node.
A TTL tri-state bus generally has several sets of drivers/receivers connected to it. Each of the driver/receivers connected to a bus can be put in active drive or tri-state modes by asserting the proper input signal on an associated "Tri-State Control" circuit. Such a tri-state control function is a normal part of the TTL tri-statable driver.
Conventional bus design practice requires that, at any given time, only one set of drivers is active on the bus. Prior to enabling one set of drivers to the active drive mode, all other drivers must be tri-stated. This ensures that bus contention does not occur.
The speed with which drivers can be put into or taken out of tri-state mode directly affects the functional performance of the bus. The speed of the transition between "tri-state" and "active" modes determines the speed of the multiplexing operation. The delay involved in such transitions is a major limitation in the design of high speed systems using conventional TTL technology.
In conventional TTL tri-state control design, a TTL signal is used to drive the control circuitry. Also, the control circuit itself is based on conventional TTL design methods. The delay performance of such a control circuit is relatively poor.
In the conventional integrated circuit situation where a true ECL circuit is used to drive a true TTL tri-state bus, the approach is as follows: True ECL signals are those that are internal to the chip and are first translated to internal true TTL signals. These true TTL levels are buffered and then used a input to the tri-state control circuit, which either tri-states or activates the I/0 driver it controls. This technique "costs" two output cells worth of power and density. It is also quite slow since the ECL tri-state signal is first translated into a TTL signal via a conventional translator circuit, then buffered, and finally input to the control circuit. The series delay of the translator and buffer circuits added to the tri-state input makes the "tri-state" to "active" mode transitions quite slow. This poor delay performance makes the use of tri-state drivers impractical in fast TTL digital designs.